Effect of Dielectric Variations on Performance of Carbon Nanotube Field Effect Transistor Based Basic Logic Gates

The continuous scaling down of feature size in Silicon technology has resulted in several technological and fundamental hindrances. The researchers started to look for new nanoscale devices those can replace CMOS transistors in digital circuits. The nanowire transistor, FinFET, Carbon Nanotube field effect transistor (CNFET), tunnel field effect transistor (TFET), and single electron transistor (SET) emerged as potential future replacement for CMOS transistors in digital circuits. CNFETs are being considered to be most promising device because of its novel properties like high current carrying capability (~ 10 10 A/cm 2 ), excellent carrier mobility, scalability, high reliability for elevated temperature operation, and negligible leakage current. Moreover CNFET has structure and mode of operation similar to CMOS transistor. This paper presents design of virtual source CNFET based basic logic gates. Then, it analyzes the effect of dielectric variations on performance parameters of carbon nanotube field effect transistor based universal gates. The performance parameters computed for designed gates are delay, power consumption, and figure-of-merit power-delay product (PDP). H-SPICE simulator has been used for simulations using Stanford University Virtual-Source CNFET model. Comparison between CMOS and CNFET based logic circuits is carried out for different dielectric material at 16nm technology node.